1. Field of the Invention
The present invention relates to a semiconductor memory and more particularly, relates to an arrangement of a memory array of a dynamic random access memory.
2. Description of the Prior Art
In a typical single transistor type of metal oxide semiconductor dynamic random access memory, the binary information "1" and "0" corresponds to the presence and absence of a charge to be stored in a metal oxide semiconductor capacitor, respectively. Such a semiconductor memory is adapted such that a charge stored in a metal oxide semiconductor capacitor is transferred to a bit line by turning a transfer gate on and a small change of the voltage caused at that time in the bit line by the presence or absence of the stored charge is detected by a sense amplifying circuit.
Since a plurality of bit lines and a plurality of word lines constituting transfer gates are closely disposed in a matrix manner in X and Y directions which are orthogonal to each other, selection of materials for these lines is a very important factor for constituting a memory array.
FIGS. 1A and 1B are a plan view and a cross sectional view, respectively, for explaining a prior art memory cell wherein a bit line is formed of an N.sup.+ diffusion region and a word line is formed of a metal. The memory cell comprises an N.sup.+ diffusion region 1 constituting a bit line, a first polysilicon layer 2 constituting a cell plate, a second polysilicon layer 3 constituting a transfer gate, an aluminium layer 4 constituting a work line, and a contact hole 5 for providing a word line signal to the transfer gate. Such structure has a shortcoming that the length of the transfer gate may often be different from transfer gate to transfer gate because self-alignment of the first and second polysilicon layers 2 and 3 is impossible or very difficult.
FIG. 2 shows an example of a memory array which is arranged by using memory cells shown in FIG. 1. Such a prior art memory array was necessarily of an open bit line structure wherein bit lines BL and bit lines BL are disposed on both sides of the sense amplifier circuit 6, respectively. More particularly, such an open bit line structure as shown in FIG. 2 comprises a plurality of sense amplifiers 6, a plurality of left word lines LWL disposed on the left side of the corresponding sense amplifier, a plurality of right word lines RWL disposed on the right side of the corresponding sense amplifiers. These word lines LWL and RWL are connected to the corresponding memory cell 8. The open bit line structure further comprises a pair of left dummy cells 7L, a pair of right dummy cells 7R, a left dummy word line LD and a right dummy word line RD. The dummy word lines LD and RD are connected to corresponding dummy cells 7L and 7R, respectively. The capacity of the dummy cells 7L and 7R are approximately half of the capacity of the memory cell. The contents of the memory cells 8 are read out by word signals on the word lines LWL and RWL. At the same time, the contents of the dummy cells 7L or 7R are read out by a word signal on a dummy word line LD or RD. These word signals are supplied from a word driving circuit 10. For example, if and when the information stored in the memory cell 8a is read out, word signals are applied from the word driving circuit 10 to the word line LWLa and the dummy word line RD. The outputs from the memory cell 8a and the dummy cell 7R are differentially amplified and detected by the sense amplifying circuit 6 (SA2). However, such open bit line structure has a disadvantage that it erroneously operates when a common mode noise is applied to only the left or right bit line.
FIGS. 3A and 3B are a plan view and a cross sectional view for explaining another prior art memory cell wherein a bit line is formed of an aluminium layer and a word line is formed of a polysilicon layer. Such memory cell comprises an aluminium layer 11 constituting a bit line, a first polysilicon layer 12 constituting a cell plate, a second polysilicon layer 14 constituting a word line and a contact hole 15 connecting a bit line to a memory cell. FIG. 4 shows an example of a memory array which is arranged by memory cells 18 shown in FIG. 3. This example is of a folded bit line structure wherein bit lines BL and bit lines BL are disposed on the same side of sense amplifying circuits 6. Thus, word lines WL, dummy word lines DW1 and DW2, bit cells 18 and dummy cells 17 are also disposed on the same side of the sense amplifying circuits 6. It is well-known that, as compared with an open bit line structure as shown in FIG. 2, the folded bit line structure is immune to a common mode noise and thus is suitable for a high density random access memory which is necessary to detect a small signal. On the other hand, in case where word lines 14 are formed of polysilicon layers 3 as shown in FIGS. 3 and 4, such folded bit line structure is not suitable for fast operation since an RC time constant of a polysilicon word line becomes larger than that of an aluminium word line. In order to avoid such problems, conventionally, a length of word line WL formed of a polysilicon layer 14 is made shorter by dividing a memory array, or a word line is formed of a metal having a high melting point, such as Mo. However, in the former approach, a chip size becomes very large and in the latter approach, mass production is very difficult.
For the purpose of decreasing imbalance of noise in a folded bit line structure, a double cells/1 bit or twin cell system has been proposed. FIG. 5 shows one example of such twin cell system. Such a twin cell system is adapted such that no dummy word lines are required and that if and when one word line is selected from a plurality of word lines WL formed of polysilicon layers 14, two memory cells 18a and 18b are selected which store data in a complementary manner per a signal sense amplifying circuit 6, the complementary data from these two memory cells 18a and 18b being transferred to bit lines BL and bit lines BL through equal bit line length and entered to the sense amplifying circuit 6. For this reason, the imbalance, such as a delay of signal and the like, between a word line and a dummy word line can be completely eliminated. Nevertheless, a prior example as shown in FIG. 5 is not suitable for a fast operation since an RC time constant of a polysilicon word line is relatively large.